1. Field of the Invention
The present invention relates generally to an information signal restoring apparatus which is arranged to restore a modulated information signal, formed by modulating a predetermined carrier signal in accordance with an information signal, to the original information signal.
2. Description of the Related Art
Electronic still video systems of the type which are arranged to record, for example, still image signals on and reproduce them from magnetic discs have heretofore been known. Such an electronic still video system is typically arranged so that index (ID) data representing information concerning a date and time corresponding to the still image signal is recorded on a magnetic disc together with the still image signal.
The ID data is recorded on the magnetic disc by the method including the steps of modulating a corresponding ID signal by a known DPSK process (differential phase-shift keying process) using a signal (13f.sub.H) of frequency thirteen times as high as that of a horizontal synchronizing signal and multiplexing the ID signal of the differentially phase-shift keyed form with a concerning still image signal. If the ID signal thus recorded is to be reproduced, a demodulator such as that shown in FIG. 1 is used for purposes of demodulation.
FIG. 1 is a schematic block diagram of a conventional type of demodulator for demodulating a so-called two-phase DPSK signal, and FIG. 2 is a timing chart showing waveforms appearing at the various points shown in FIG. 1.
The demodulator shown in FIG. 1 includes the following major elements: an input terminal 1 at which a DPSK signal is provided, a shift register 2, an exclusive OR (EXOR) circuit 3, a low-pass filter (LPF) 4, a buffer amplifier 5 and an output terminal 6 at which a demodulated version of the DPSK signal is provided.
The DPSK signal, which is provided at the input terminal 1, has the waveform shown in Part (a) of FIG. 2, and serves to transmit one bit of data in each period indicated by T in the same part. This signal of Part (a) is read into the shift register 2 in accordance with a clock which is input thereto through a terminal 7, the clock being shown in Part (g) of FIG. 2.
The number of bits of the shift register 2 is determined as follows: EQU N=T/t(T&gt;t)
where N represents the number of bits and t represents the period of the clock (g). It follows, therefore, that the DPSK signal is delayed by the period T by the shift register 2. The output signal from the shift register 2, shown in Part (b) of FIG. 2, and the input DPSK signal shown in Part (a) are input to the EXOR circuit 3, and the EXOR circuit 3 provides the output signal shown in Part (c) of FIG. 2. This signal of Part (c) passes through the LPF 4, where it is converted into a demodulated signal having the waveform shown in Part (e) of FIG. 2. The waveform of this signal is then shaped by the buffer amplifier 5 to provide a demodulated signal of the DPSK signal, which has the waveform shown in Part (f) of FIG. 2.
As is known, the aforesaid DPSK signal serves to represent one bit of information in accordance with whether or not the phase of the aforesaid signal of frequency 13f.sub.H is reversed every 4H or 2H period (H: horizontal synchronizing period). Accordingly, the conventional demodulator consecutively detects the phase state of the DPSK signal throughout the 4H or 2H period, and restores binary information "1" if the state of phase reversal lasts for a time period which is longer than or equal to half the 4H or 2H period and, restores binary information "0" if such a state lasts for a time period which is shorter than the same period.
However, the above-described type of apparatus, commonly arranged so that the 4H or 2H period during which detection of the phase state is performed, is specified in synchronization with a horizontal synchronizing signal multiplexed with the DPSK signal. However, the DPSK signal is susceptible to signal deterioration due to phase fluctuations, level attenuation or the like during certain time periods which last before and after each horizontal synchronizing signal appears. Accordingly, it is difficult to stably detect the phase state during such a time period, thus resulting in the likelihood that restored information may contain errors.
In addition, the conventional apparatus has the problem that its circuit scale must be increased because of the following reason.
In the electronic still video system which employs a carrier signal of frequency 13f.sub.H as described previously, one bit of information is represented with four or two horizontal synchronizing signals. Accordingly, one bit of information may be represented with horizontal synchronizing signals corresponding to the maximum 52 periods (4.times.13).
However, if such signals are to be stored in the form of a waveform, sampling needs to be repeated at least five times per period and a shift register of 260 stages (52.times.5) is therefore required as the shift register 2 of FIG. 1.
If such a 260-stage shift register is to be realized, two hundred and sixty D-flip-flops are needed as shown by, for example, F.sub.1 -F.sub.260 in FIG. 3. As a result, the circuit scale becomes excessively large and an increase in cost will be incurred.